Synchronous dynamic random access memory (SDRAM) chips are produced in a variety of storage capacities including, 128-Mbit, 256-Mbit, and 512-Mbit. In general, each memory chip includes at least one array of memory cells. The memory cells are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Conductive word lines extend across the array of memory cells along the x-direction and conductive bits lines extend across the array of memory cells along the y-direction. A memory cell is located at each cross point of a word line and bit line. Memory cells are accessed using a row address and a column address.
Memory chips are often manufactured with larger storage capacities and reduced to smaller storage capacities for sale. Reducing the storage capacity can occur for a number of reasons, including the chip contains more memory cell defects than can be repaired using normal redundancy techniques or a smaller capacity memory chip provides a larger profit margin.
For memories with storage capacities such as 128-Mbit and 256-Mbit storage capacities, doubling the storage capacity of the memory means doubling the number of memory cells. The additional memory cells can be addressed by doubling the number of rows. An additional row address bit is therefore required. For these memories, it is simple to halve the storage capacity by shorting the most significant row address bit to either a logic high level or a logic low level. If the most significant row address bit is shorted to a logic high level, the lower half of the memory is disabled. If the most significant row address bit is shorted to a logic low level, the upper half of the memory is disabled. For example, to disable the lower half of a 256-Mbit chip, the most significant row address bit is shorted to a logic low level, resulting in a 128-Mbit chip.
For conforming memories with 512-Mbit storage capacities and higher (i.e. one that complies with Joint Electron Device Engineering Council (JEDEC) standards), the addressable cells are doubled by doubling the number of columns and adding an additional column address, rather than adding rows. A conforming 512-Mbit chip has a page length of 16 k bits (equal to the number of columns) while a conforming 256-Mbit chip has a page length of 8 k bits. Therefore, simply shorting the most significant row address bit to a logic high level or logic low level to reduce the addressable memory cells results in a nonconforming SDRAM. Nonconforming memory chips cannot be sold in the commodity SDRAM market. For example, if a 512-Mbit chip is reduced to a 256-Mbit chip by shorting the most significant row address bit to a logic high level or logic low level, the resulting 256-Mbit chip still has a page length of 16 k bits, which is nonconforming.
In addition, shorting the most significant column address bit of a 512-Mbit chip to a logic high level or a logic low level results in a chip in which array addressing can conflict with data pad organizations. SDRAM chips typically have one die solutions for multiple data pad (DQ) organizations. Depending upon whether the memory chip has 4, 8, or 16 DQs (x4, x8, x16 DQ organization), the number of column address bits will vary. For example, assuming a 512-Mbit DDR SDRAM with x16 organization, 16 k array cells are connected to an activated row and 32 bits are addressed per memory access. Therefore, nine column address bits are needed to access all the data in one row. For a 512-Mbit DDR SDRAM with x8 organization, ten column address bits are needed to access all the data in one row. The most significant column address bit depends on the DQ organization. To short the most significant column address bit to a logic high level or a logic low level would require coordination with the DQ organization.
A lower column address bit can be shorted to a logic high level or a logic low level to reduce the size of the addressable memory, but this has several disadvantages. Using a lower column address bit limits the addressable block size. Limiting the addressable block size limits the size of cluster fails that can be bypassed as a cluster fail could extend beyond one block. In addition, using a lower column address bit can interfere with or destroy normal column redundancy techniques, as a redundant column could be located in a deactivated section leaving a column in an addressable section without a redundant column.